Electrostatic discharge (ESD) is a dominant reliability concern in the semiconductor industry. The failure susceptibility of integrated circuits (ICs) to ESD increases as the IC technology progresses towards submicron feature lengths. ESD protection for input, output and/or power supply pins in advanced CMOS ICs is achieved by a protection network that shunts the protected pin and the ground bus under stress events. For input pins, a dedicated protection network that is completely passive under normal operating conditions is added to the input's functional circuitry.
There are a variety of silicon controlled rectifier (SCR) devices available for ESD protection of complementary metal-oxide-semiconductor (CMOS) I/O pins. A SCR is a device having four alternate layers of n and p type silicon which functions as a current controlled switch. A SCR normally acts as an open circuit but switches rapidly to a conducting state when an appropriate signal (such as an ESD event) is applied to the gate terminal. One standard protection device is the lateral SCR structure consisting of a vertical PNP and a lateral NPN, as shown in FIG. 1. The vertical PNP consists of p+ diffused region 22, n-well 18, and P-type substrate 14. Substrate 14 is connected to ground GND and p+ diffused region 22 is connected to pad 12. N-well 18 is also connected to the pad 12 through n+ diffused region 24. The lateral NPN consists of n-well 18, p-substrate 14 and n+ diffused region 20. N+ diffused region 20 is connected to ground. Field oxide region 16 separates p+ diffused region 22 and n+diffused region 20 at the boundary of n-well 18. The p+ diffused region 22 in n-well 18 forms the anode of the SCR. The cathode of the SCR is formed by n+ diffused region 20 connected to ground.
The trigger mechanism of the protection device is usually the breakdown of the NPN, followed by the turn on of the vertical PNP. However, for voltage applications, the range of operation is restricted to -0.5 V to +V.sub.triger. The +V.sub.trigger, is determined by the SCR design and the -0.5 V is limited by the inherent forward biased diode the n+ region 24 connection and the p-substrate 14.